A basic building block employed in many analog and mixed-signal electronic systems is the summing amplifier, or summer, which adds together two or more analog signals. At lower frequencies, an accurate summer can be realized as a closed-loop circuit based around a high-gain operational amplifier. However, the need to maintain feedback loop stability does entail compromises in the bandwidth of a closed-loop amplifier, so open-loop summing amplifiers are usually a more practical choice at very high signal frequencies (e.g., above 1 GHz).
While open-loop summing amplifiers can be employed to advantage in many high-frequency applications, ranging from radio and radar signal processing to high-speed data conversion, the example chosen here to illustrate the utility of such a circuit block is a decision-feedback equalizer (DFE) used to improve the reception of multi-gigabit-per-second serial data. Due to limited channel bandwidth, the electrical pulses (representing bits) transmitted over a serial link are broadened over more than one unit interval (UI), and the received signal suffers from intersymbol interference (ISI). The ISI from previous bits in the data stream can be effectively compensated if the receiver circuitry includes a DFE, whose block diagram is shown in FIG. 1.
In DFE 100, the previously decided bits are delayed via latches 106-2 through 106-N and fed back with weighted tap coefficients (H1, H2, . . . , HN) by way of feedback circuits 108-1 through 108-N. They are then added to the received input signal with analog summing amplifier 102. Because the input signal and the feedback signals are all high speed (i.e., multi-GHz), this analog summer is typically an open-loop amplifier. Examples of such summers may be found in T. Beukema et al., “A 6.4-Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization,” IEEE J. Solid-State Circuits, Vol. 40, pp. 2633-2645, December 2005; and R. Payne et al, “A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels,” IEEE J. Solid-State Circuits, Vol. 40, pp. 2646-2657, December 2005.
If the magnitudes and polarities of the tap weights are properly adjusted to match the channel characteristics, the ISI from earlier bits in the data stream will be canceled, and the bits can be detected by data slicer 104 with a low bit error rate (BER). The adjustment of the tap weights can be performed either manually or automatically by an appropriate adaptive algorithm. A fundamental advantage of a DFE over a simple linear equalizer is that the ISI is compensated without amplifying noise or crosstalk.
High-speed signal summation is easily accomplished in the current domain by connecting together (“dotting”) the drains (or collectors if implemented in bipolar technology) of multiple differential pairs of transistors. In most past designs, the summed currents are converted into voltages by load resistors. A drawback of such resistive loading is relatively high power dissipation. A critical timing requirement for a DFE is that the feedback signals must settle accurately at the slicer input before the next data decision is made. To ensure fast enough settling, the RC time constant at the summer output nodes must be much smaller than one UI (e.g., 100 picosecond at 10 gigabits per second). The wiring and device parasitic capacitances all contribute to the total capacitance C. Even with optimum layout techniques, there is a lower limit to the achievable capacitance C, so the only practical way of achieving a small enough RC time constant is to reduce the load resistance R to a low value. To meet amplifier gain and voltage swing requirements, however, the reduction in R must be accompanied by a commensurate increase in operating currents, leading to higher power dissipation.
A more power-efficient summing amplifier can be implemented as a current integrator, in which the aforementioned load resistors are replaced by resettable capacitors. For highest power efficiency, the capacitors can be just C, the parasitic capacitances of the wiring and devices, see, e.g., S. Sidiropoulos et al., “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers,”IEEE J. Solid-State Circuits, Vol. 32, pp. 681-690, May 1997. Integrating currents on parasitic capacitances is fundamentally much more power efficient than resistive current-to-voltage conversion. In the resistive scheme, the resistance value is deliberately chosen to be low enough that its impedance is much less than that of the parasitic capacitance over all frequencies of interest. This directly follows from the earlier requirement that the RC time constant be much less than one UI. Consequently, much higher operating currents are needed to generate the same output voltage levels with resistive loads. With typical circuit parameters, the power dissipation of a current-integrating summer may be almost an order of magnitude lower than that of a resistively loaded summer.
An important penalty of integrating currents onto parasitic capacitances is that the output voltage levels of the summer are highly sensitive to process variations. In addition, the output voltage levels depend on the integration time, which may need to be varied in some applications (such as a DFE receiving data with different bit rates). To realize a current-integrating summing amplifier with well-defined output voltage levels, it is desirable to have a calibration circuit which compensates for these sources of variability.
The above-referenced S. Sidiropoulos et al. article describes a calibration circuit based on replica feedback biasing which stabilizes the output voltage levels of a current integrating receiver with a single input. In the replica bias circuit, a large differential voltage is applied to a replica integrator stage so that its input differential pair is fully switched, steering all of its tail current to one of its output (i.e., drain) nodes. At the end of an integration period, the voltage at this node is sampled and compared to a reference voltage. If the sampled voltage is lower than the reference voltage, a feedback loop based on an operational amplifier boosts the tail current of the integrator, so that the integrated output voltage increases. If the sampled voltage is higher than the reference voltage, the feedback loop drops the tail current of the integrator, so that the integrated output voltage decreases. Once the feedback loop has stabilized, the sampled voltage matches the desired reference voltage. Since the bias voltage for the tail current is shared with the integrator stage receiving the actual data input signal, the output voltage levels of this stage are stabilized as well.
While the replica feedback biasing scheme described in S. Sidiropoulos et al. does stabilize the output voltage levels of an integrating receiver with a single input, a circuit for calibrating a current-integrating summing amplifier with multiple inputs has not been shown to date. While a DFE based on a current-integrating summer is described in S.-J. Bae et al., “A 2 Gb/s 2-Tap DFE Receiver for Multi-Drop Single-Ended Signaling Systems with Reduced Noise,” ISSCC Dig. Tech. Papers, pp. 244-245, February 2004, no provision for calibrating its output voltage levels is described therein.
Accordingly, it would be desirable to provide improved techniques for calibrating summing amplifiers based on current integration.